PCB layout design skills of non-isolated switching power supply

A good layout design can optimize efficiency, reduce thermal stress, and minimize the noise and effect between traces and components. All this stems from the designer’s understanding of the current conduction path and signal flow in the power supply.

A good layout design can optimize efficiency, reduce thermal stress, and minimize the noise and effect between traces and components. All this stems from the designer’s understanding of the current conduction path and signal flow in the power supply.

When a prototype power board is powered on for the first time, the best case is that it not only works, but it is also quiet and has low heat. However, this situation is rare.

A common problem with switching power supplies is “unstable” switching waveforms. Sometimes, the waveform jitter is in the sound band, and the magnetic components will produce audio noise. If the problem lies in the layout of the printed circuit board, it may be difficult to find the cause. Therefore, the correct PCB layout at the initial stage of switching power supply design is very critical.

The power supply designer must have a good understanding of the technical details and the functional requirements of the final product. Therefore, from the beginning of the circuit board design project, the power supply designer should work closely with the PCB layout designer on the key power supply layout.

A good layout design can optimize power efficiency and reduce thermal stress; more importantly, it minimizes noise and the interaction between traces and components. To achieve these goals, designers must understand the current conduction path and signal flow inside the switching power supply. To realize the correct layout design of non-isolated switching power supply, the following design elements must be kept in mind.

PCB layout design skills of non-isolated switching power supply

For the embedded dc/dc power supply on a large circuit board, in order to obtain the best voltage regulation, load transient response and system efficiency, it is necessary to make the power output close to the load device and minimize the interconnection impedance and conduction on the PCB trace Pressure drop. Ensure that there is a good air flow to limit thermal stress; if forced air cooling measures can be used, the power supply should be close to the fan.

In addition, large passive components (such as inductors and electrolytic capacitors) must not block air flow through low surface-mounted semiconductor components, such as power MOSFETs or PWM controllers. To prevent switching noise from interfering with the analog signals in the system, you should avoid placing sensitive signal lines under the power supply as much as possible; otherwise, you need to place an internal ground layer between the power layer and the small signal layer for shielding.

The key is to plan the location of the power supply and the need for board space in the early design and planning stages of the system. Sometimes designers ignore this advice and focus on the more “important” or “exciting” circuits on the large system board. Power management is regarded as an afterthought, and the power is placed on the extra space on the circuit board. This approach is very detrimental to high-efficiency and reliable power supply design.

For multi-layer boards, a good method is to place a DC ground or DC input/output voltage layer between the high-current power component layer and the sensitive small-signal trace layer. The ground layer or DC voltage layer provides an AC ground shielding small signal traces to prevent interference from high-noise power traces and power components.

As a general rule, neither the ground plane nor the DC voltage plane of a multilayer PCB should be separated. If this separation is unavoidable, try to reduce the number and length of the traces on these layers, and the layout of the traces should be kept in the same direction as the high current to minimize the impact.

PCB layout design skills of non-isolated switching power supply

Figures 1a and 1c show the poor layer structure of a six-layer and four-layer switching power supply PCB, respectively. These structures sandwich the small signal layer between the high current power layer and the ground layer, thereby increasing the capacitive noise coupled between the high current/voltage power layer and the analog small signal layer.

1b and 1d in the figure are good structures for six-layer and four-layer PCB designs, which help minimize interlayer coupling noise. The ground layer is used to shield the small signal layer. The main point is: A ground layer must be placed next to the outer power level layer, and thick copper foil should be used for the external high-current power layer to minimize PCB conduction loss and thermal resistance.

Power stage layout

The switching power supply circuit can be divided into two parts, the power stage circuit and the small signal control circuit. The power stage circuit contains components used to transmit large currents. Generally, these components should be placed first, and then small-signal control circuits should be placed at specific points in the layout.

High-current traces should be short and wide to minimize PCB inductance, resistance, and voltage drop. For those traces with high di/dt pulse currents, this aspect is especially important.

PCB layout design skills of non-isolated switching power supply

Figure 2 shows the continuous current path and pulse current path in a synchronous buck converter. The solid line represents the continuous current path, and the dashed line represents the pulse (switch) current path. The pulse current path includes traces connected to the following components: input decoupling ceramic capacitor CHF, upper control FET QT and lower synchronous FET QB, as well as optional parallel Schottky diodes.

Figure 3a shows the PCB parasitic inductance in the high di/dt current path. Due to the parasitic inductance, the pulse current path not only radiates magnetic fields, but also generates large voltage ringing and spikes on the PCB traces and MOSFETs. In order to minimize the PCB inductance, the pulse current loop (the so-called thermal loop) should have a minimum circumference when laying out, and its trace should be short and wide.

The high frequency decoupling capacitor CHF should be 0.1μF~10μF, X5R or X7R dielectric ceramic capacitor, it has very low ESL (effective series inductance) and ESR (equivalent series resistance). Larger capacitor dielectrics (such as Y5V) may cause the capacitance value to drop significantly at different voltages and temperatures, so it is not the best material for CHF.

Figure 3b provides a layout example for the key pulse current loop in a buck converter. In order to limit the resistance voltage drop and the number of vias, the power components are placed on the same side of the circuit board, and the power traces are also placed on the same layer. When a certain power cord needs to be routed to other layers, a route in the continuous current path should be selected. When using vias to connect the PCB layer in a high-current loop, use multiple vias to minimize impedance.

PCB layout design skills of non-isolated switching power supply

Figure 4 shows the continuous current loop and the pulse current loop in the boost converter. At this time, a high-frequency ceramic capacitor CHF should be placed close to the output end of the MOSFET QB and the boost diode D.

PCB layout design skills of non-isolated switching power supply

Figure 5 shows the thermal loop and parasitic PCB inductance in the boost converter (a); the recommended layout to reduce the thermal loop area (b)

Figure 5 is an example of the layout of the pulse current loop in the boost converter. At this time, the key is to minimize the loop formed by the switching tube QB, the rectifier diode D and the high-frequency output capacitor CHF. Figure 6 provides an example of a synchronous step-down circuit, which emphasizes the importance of decoupling capacitors.

Figure 6a is a dual-phase 12VIN, 2.5VOUT/30A (maximum) synchronous step-down power supply, using the LTC3729 dual-phase single VOUT controller IC, when there is no load, the waveforms of the switch nodes SW1 and SW2 and the output Inductor current All are stable (Figure 6b). But if the load current exceeds 13A, the waveform of the SW1 node begins to lose cycles. When the load current is higher, the problem gets worse (Figure 6c).

PCB layout design skills of non-isolated switching power supply

Adding two 1μF high-frequency ceramic capacitors to the input of each channel can solve this problem. The capacitor isolates the thermal loop area of ​​each channel and minimizes it. Even under the maximum load current up to 30A, the switching waveform is still very stable.

High DV/DT switch area

In Figure 2 and Figure 4, the SW voltage swing between VIN (or VOUT) and ground has a high dv/dt rate. There are abundant high-frequency noise components on this node, which is a powerful source of EMI noise. In order to minimize the coupling capacitance between the switch node and other noise-sensitive traces, you may make the SW copper foil area as small as possible. However, in order to conduct a large inductor current and provide a heat dissipation area for the power MOSFET, the PCB area of ​​the SW junction cannot be too small. It is generally recommended to place a grounded copper foil area under the switch node to provide additional shielding.

If there is no heat sink for surface mount power MOSFET and inductor in the design, the copper area must have enough heat dissipation area. For DC voltage junctions (such as input/output voltage and power ground), a reasonable method is to make the copper area as large as possible.

More vias help to further reduce thermal stress. To determine the appropriate copper area of ​​the high dv/dt switch junction, it is necessary to make a design balance between minimizing dv/dt related noise and providing good MOSFET heat dissipation capabilities.

Power pad form

Pay attention to the pad form of power components, such as low ESR capacitors, MOSFETs, diodes, and inductors.

For decoupling capacitors, the positive and negative vias should be as close as possible to each other to reduce the ESL of the PCB. This is especially effective for low ESL capacitors. Capacitors with small capacitance and low ESR are usually more expensive, and incorrect pad patterns and poor wiring will reduce their performance and increase overall cost. Under normal circumstances, a reasonable pad form can reduce PCB noise, reduce thermal resistance, and minimize trace impedance and voltage drop of high-current components.

A common misunderstanding in the layout of high-current power components is the incorrect use of thermal relief. The use of hot air pads in unnecessary cases will increase the interconnection impedance between power components, resulting in greater power loss and reducing the decoupling effect of small ESR capacitors. If you use vias to conduct large currents during layout, make sure they have a sufficient number to reduce impedance. In addition, do not use hot air pads for these vias.

Keep the control circuit away from the high-noise switch copper foil area. For a buck converter, a good approach is to place the control circuit close to the VOUT+ terminal, while for a boost converter, the control circuit should be close to the VIN+ terminal to allow the power traces to carry continuous current.

If space permits, there should be a small distance (0.5 inch to 1 inch) between the control IC and the power MOSFET and inductor (they are high noise and high heat components). If the space is tight and the controller is forced to be placed close to the power MOSFET and the inductor, special attention should be paid to the use of ground or ground wiring to isolate the control circuit from the power components.

The control circuit should have an independent signal (analog) ground that is different from the power stage ground. If there are separate SGND (signal ground) and PGND (power ground) pins on the controller IC, they should be wired separately. For the control IC with integrated MOSFET driver, the IC pins of the small signal part should use SGND.

Only one connection point is needed between signal ground and power ground. A reasonable method is to return the signal ground to a clean point in the power formation. Only by connecting two grounding traces under the controller IC, two grounds can be realized.

The decoupling capacitors of the control IC should be close to their respective pins. In order to minimize the connection impedance, a good method is to connect the decoupling capacitor directly to the pin without passing through the via.

Loop area and crosstalk

Two or more adjacent conductors can be capacitively coupled. The high dv/dt on one conductor will couple current through the parasitic capacitance on the other conductor. In order to reduce the coupling noise of the power stage to the control circuit, high-noise switch traces should be kept away from sensitive small-signal traces. If possible, place high-noise traces and sensitive traces on different layers, and use the internal ground layer as a noise shield.

If space permits, the control IC should have a small distance (0.5 inch to 1 inch) from the power MOSFET and the inductor, the latter has both large noise and heat generation.

The FET drivers TG, BG, SW and BOOST pins on the LTC3855 controller all have high dv/dt switching voltages. The LTC3855 pins connected to the most sensitive small signal node are: Sense+/Sense-, FB, ITH and SGND. Insert a ground wire or ground layer between high dv/dt traces to shield noise.

When laying out the gate drive signal, using short and wide traces helps to minimize the impedance in the gate drive path.

If a PGND layer is placed under the BG trace, the AC ground return current of the low FET will automatically couple to a path close to the BG trace. AC current will flow to the smallest loop/impedance it finds. At this time, the low gate driver does not need a separate PGND return trace. The best way is to minimize the number of layers through which the gate drive traces pass, so as to prevent the gate noise from spreading to other layers.

Among all the small signal traces, the current detection traces are the most sensitive to noise. The amplitude of the current detection signal is usually less than 100mV, which is equivalent to the amplitude of noise. Taking LTC3855 as an example, the Sense+/Sense- traces should be placed in parallel with the smallest spacing (Kelvin detection) to minimize the chance of picking up di/dt related noise.

In addition, the filter resistors and capacitors of the current detection traces should be as close as possible to the IC pins. This structure has the best filtering effect when noise is injected into the long detection line. If the inductor DCR current detection method with R/C network is used, the DCR detection resistor R should be close to the inductor, and the DCR detection capacitor C should be close to the IC.

If a via is used on the return path from the trace to the Sense-, the via should not touch other internal VOUT+ layers. Otherwise, the via hole may conduct a large VOUT+ current, and the resulting voltage drop may destroy the current detection signal. Avoid placing current detection traces near high-noise switching nodes (TG, BG, SW, and BOOST traces). If possible, place a ground plane between the layer where the current sensing trace is located and the power stage trace layer.

If the controller IC has a differential voltage remote detection pin, use separate wiring for the positive and negative remote detection lines, and also use the Kelvin detection connection.

For specific controller pins, current levels and noise sensitivity are unique, so specific trace widths must be selected for different signals. Under normal circumstances, small signal networks can be narrower, using 10mil~15mil width traces; high current networks (gate drive, VCC, and PGND) should use short and wide traces. The traces of these networks are recommended to be at least 20mil wide.

The Links:   MDT1200-18E LQ035Q3DW02 SEMIKRONIGBT

Leave a Reply

Your email address will not be published.