Lattice Propel allows designers to complete designs quickly

“Almost all Electronic designers and embedded system developers have heard of Field Programmable Gate Array (FPGA). For the actual FPGA device, designers and developers know that it has a programmable architecture that can be configured to perform the desired functions, but their understanding may be limited to this. Similarly, when it comes to creating a design that can be implemented on an FPGA, they may have heard terms such as hardware description language (HDL) and register conversion level circuit (RTL), but may not fully understand their meaning.

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Almost all electronic designers and embedded system developers have heard of Field Programmable Gate Array (FPGA). For the actual FPGA device, designers and developers know that it has a programmable architecture that can be configured to perform the desired functions, but their understanding may be limited to this. Similarly, when it comes to creating a design that can be implemented on an FPGA, they may have heard terms such as hardware description language (HDL) and register conversion level circuit (RTL), but may not fully understand their meaning.

Similar to Verilog or VHDL, HDL allows FPGA designers to describe design intent, just as software developers use programming languages ​​such as C or C++. One of the ways to understand HDL is that it can be used to describe things that happen at the same time, which is how hardware works in the real world. In contrast, software programming languages ​​are often used to describe things that happen sequentially.

At the same time, RTL is an abstract level circuit often used for the input of logic synthesis engines. This tool converts RTL to logic elements and interconnection networks, and then implements them in the programmable logic of the FPGA. A logic synthesis engine can be compared to a software developer’s compiler, which takes high-level programs as input and converts them into machine code executed by the processor.

The programmable structure of FPGA can be used to build hardware accelerators to perform data processing tasks with low power consumption. The programmable structure can be configured to create one or more soft-core processors that are more suitable for processing decision-making tasks. These processors can also control hardware accelerators, including providing data to them and taking corresponding measures based on the results.

RISC-V is such a processor, it is an open source instruction set architecture (ISA), which can be obtained free of charge through an open source license. The creators of the RISC-V open source hardware concept were inspired by the success of Linux open source software. One of the great advantages of RISC-V is that it has excellent software compatibility in various design implementations, and the use of these processors is currently increasing rapidly.

However, for non-FPGA designers who want to use such processors, the problem is that they lack expertise in FPGA design languages, tools, and processes. To solve this problem, Lattice semiconductor, a leading supplier of low-power programmable FPGAs, has developed a tool called Lattice Propel™, which is a graphical user interface (GUI)-based design environment that allows any user (with or without FPGA expertise) can use it to quickly design systems based on RISC-V processors in a drag-and-drop manner.

The output of Propel is an RTL file, which can be sent to the synthesis engine to generate a configuration file that can be loaded into the FPGA. Afterwards, software developers can run their RISC-V executable files on FPGA-based RISC-V design implementations, just as they run on any other RISC-V processor. Lattice provides its FPGA customers with RISC-V IP cores for free.

FPGA-based solutions

Data processing requires a suitable calculation engine. Developers have many different choices, including devices such as microprocessors (MPU), microcontrollers (MCU), graphics processing units (GPU), FPGAs, and SoCs.

MPU and MCU are very efficient in performing decision-making tasks, but when implementing original data processing algorithms, both processing time and power consumption are not ideal. SoC can achieve the highest performance with the lowest power consumption, but the disadvantage is that it is expensive to develop, consumes resources and is very time-consuming, and the algorithms implemented in this type of chip architecture are basically fixed and cannot be changed, and the protocol used by the system And standards will continue to change, so many problems will arise.
Certain data processing tasks (including many AI/ML algorithms) are very suitable for parallel processing. The FPGA’s programmable architecture (Figure 1a) can be configured to implement hardware accelerator (HA) functions to perform tasks in a massively parallel manner (Figure 1b), thereby significantly improving performance while reducing power consumption.

In many cases, data co-processing functions are also required. The central processing unit (CPU) is used to enhance the hardware accelerator, and the processor can perform advanced decision-making and control functions. Different from the hard-core CPU directly implemented in the chip, the programmable architecture of FPGA can realize the soft-core CPU and the related bus structure (address, data, control) and any required peripheral IP functions (Figure 1c).

Figure 1. The structured bus approach is widely applicable to various applications, including embedded vision, security, and artificial intelligence.

It should be noted that, according to the requirements of FPGA devices and users, additional programmable logic functions and peripheral communication functions (such as USB, MIPI, I2C, SPI, CAN, and UART) can be implemented through hard cores and/or soft cores. The article is limited in length and will not be repeated here.

There are many advantages to using a soft-core CPU, including the ability to configure the operation of the processor and many optional functions, such as a dynamic memory access (DMA) controller, so that it can be precisely adjusted to efficiently meet the requirements of the target application. In addition, if necessary, a programmable structure can be configured to realize other peripheral IP functions. For example, in artificial intelligence applications, programmable logic resources can be used to create simple artificial neural networks for tasks such as reasoning.

RISC-V

As mentioned earlier, RISC-V is an open source instruction set architecture based on the existing Reduced Instruction Set Computer (RISC) principles, which can be obtained through an open source license. In addition, many companies currently provide RISC-V hard core or open source operating systems that support RISC-V, and several mainstream software tool chains support this instruction set.

The modular design of RISC-V includes a basic instruction set and other extended instruction sets. With the joint efforts of industry, technology and educational institutions, both have achieved considerable development. The basic instruction set specifies instructions (and their encoding), control flow, registers (and their sizes), memory and addressing, logic (ie integer) operations, and auxiliary functions. Only the basic instruction set can realize a general-purpose computer with comprehensive software support (including a general-purpose compiler).

Additional functions can also be realized through the optional extended instruction set, allowing designers the flexibility to choose the functions required by their applications. RISC-V defines many extended instruction sets, including A (atomic), F (single-precision floating-point), D (double-precision floating-point), Q (quad-precision floating-point) and C (compressed 16-bit instructions to reduce code Size, for systems with limited storage space). The above instruction sets can be selected flexibly.

Figure 2. Lattice is the first flash and SRAM-based FPGA supplier to support RISC-V.

Compared with the hard core implementation as a dedicated processor, the FPGA-based soft core RISC-V has a huge advantage in that the huge potential of FPGA reconfigurability can meet various expansion needs.

The Lattice RISC-V soft core IP suite has a 32-bit RISC-V processor core and optional timer and programmable interrupt controller (PIC) sub-modules. The CPU core supports RV32I instruction set, external interrupt and debugging in compliance with JTAG IEEE 1149.1 specifications.

The timer sub-module is a 64-bit real-time counter, which compares the real-time register with another register to trigger the timer interrupt. The PIC sub-module aggregates up to eight external interrupt inputs into one external interrupt. The processor core uses the industry standard 32-bit AHB-L bus interface to access the sub-module registers.

Lattice Propel

Many designers of embedded systems are interested in using FPGAs, but they are discouraged when they think of using traditional FPGA design tools and HDL. In order to solve this problem, Lattice Propel adopts a graphical user interface (GUI)-based design environment. Any user (whether with FPGA expertise or not) can use its drag-and-drop design method to quickly build and configure RISC-V The design of the processor.

What Propel outputs is an RTL file using Verilog HDL language, which can be sent to the synthesis engine to generate a configuration file that can be loaded into the FPGA. This configuration file can be used for Lattice CrossLink™-NX (for embedded vision applications), Certus™-NX (general FPGA), and MachXO3D™ and Mach™-NX FPGA (safe system control) products. After the FPGA configuration is complete, software developers can run their RISC-V executable file on the FPGA-based RISC-V design implementation, just as it runs on any other RISC-V processor.

Lattice Propel consists of two parts. The first is Propel Builder, which provides a graphical drag-and-drop interface that allows users to select IP modules and connect them together. These IP modules include RISC-V processor (with optional timer and interrupt controller), AMBA bus structure, interface, memory, input/output (I/O), etc. Users can also easily upgrade existing IP modules online and obtain new IP modules.

Figure 3. The Propel interface is intuitive, easy to use, and powerful.

In addition to drag-and-drop IP instantiation, Propel Builder can also automatically make pin connections, configure and set parameters through a wizard, and use step-by-step corrections for IP integration.

The second is the Lattice Propel SDK (software development kit), which provides a seamless software development environment. It has an industry standard integrated development environment (IDE) and tool chain. The SDK also provides software/hardware debugging functions as well as software libraries and board support packages (BSP) for the system defined by Propel Builder.

The important thing to note is that Propel can be well connected to downstream tools, and it is also an independent program, and its size is only 0.5 GB, which can be downloaded and installed quickly and easily. It is also interesting that all commands of Propel can be written in Tcl, which improves design efficiency and quickly integrates them into the user’s own design environment.

Figure 4. Whether it is a simple “Hello World” application or a complex embedded control and data processing system, Propel allows users to quickly complete the design

For hardware design, Propel is an ideal choice for teams that need FPGA advantages but lack FPGA hardware design experience. In addition, if team members do have FPGA design experience, they can also control the design more precisely as needed. For software design, Propel provides industry standard C/C++ development environment. Software developers seem to use off-the-shelf microcontrollers more.

Designers can use Propel to quickly and easily generate RISC-V soft core-based processor systems in CrossLink-NX, Certus-NX, and Mach-NX FPGAs to provide complex video processing, system control, and system security functions. The latency is much lower than the design achieved through an external independent processor.

Summarize

In addition to the logic functions and hardware accelerators that perform high-performance data processing tasks with low power consumption, the programmable architecture inside the FPGA can also be used to implement one or more soft-core processors that are more suitable for decision-making tasks, as well as for hardware accelerators such as Such control functions include providing them with data and taking actions based on the results.

RISC-V is such a processor, it is an open source instruction set architecture (ISA), which can be obtained free of charge through an open source license. Lattice is the first flash memory and SRAM-based FPGA supplier to support RISC-V and provide RISC-V IP cores for its FPGA customers free of charge.

For non-FPGA designers who want to use such processors, the problem is that they lack expertise in FPGA design languages, tools, and processes. To solve this problem, Lattice provides Propel to simplify the design process, allowing developers to quickly design systems based on RISC-V processors.